`timescale 1ns / 1ps
/*--------------------------------------------------------------------*\
FileName        : cpsm_soc.v
Author          ：hpy
Email           ：yuan_hp@qq.com
Date            ：2024年07月06日
Description     ：
\*--------------------------------------------------------------------*/
module cpsm_soc (
    input clk,
    input rst_n , 
    output wire [7:0] gpio0 ,
    output wire [7:0] gpio1 , 
    input  wire [7:0] isr  // 中断
);
 
/* ------------------ function -------------------- */
 
/* -------------------- param --------------------- */
 
/*---------------------- reg ---------------------- */

/*----------------------- wire ---------------------*/
 
/*--------------------- assign ---------------------*/

/*---------------------- blk -----------------------*/
 
//------------------------------------------------  bus 连接线 -------------------------------------------------------
                 
// bus slave 0 wire 
wire [7:0] s0_dat  ; 
wire [7:0] s0_rdt  ; 
wire [7:0] s0_adr ;  
wire s0_wen ;
wire [7:0] s0_addr;    // Slave address prefix
wire [7:0] s0_addr_msk; // Slave address prefix mask
                 
// bus slave 1 wire 
wire [7:0] s1_dat  ; 
wire [7:0] s1_rdt  ; 
wire [7:0] s1_adr ;  
wire s1_wen ;
wire [7:0] s1_addr;    // Slave address prefix
wire [7:0] s1_addr_msk; // Slave address prefix mask
                 
// bus slave 2 wire 
wire [7:0] s2_dat  ; 
wire [7:0] s2_rdt  ; 
wire [7:0] s2_adr ;  
wire s2_wen ;
wire [7:0] s2_addr;    // Slave address prefix
wire [7:0] s2_addr_msk; // Slave address prefix mask   

//------------------------------------------------  bus 地址分配 -------------------------------------------------------
assign {s0_addr , s0_addr_msk } = {8'h00 , 8'hf0} ;
assign {s1_addr , s1_addr_msk } = {8'h10 , 8'hf0} ;
assign {s2_addr , s2_addr_msk } = {8'h20 , 8'hf0} ;  


wire [7:0] out_port , port_id ; 
wire  [7:0] in_port ;
wire write_strobe  ;
wire interrupt ;
psm6_soc #(
    .memfile("cpsm_soc.hex") ,  
    .memnum ( 4096)  , 
	.stack_size  (32) ,  // 1 ~ 32 
	.scratch_size( 256), // 1 ~ 256  
    .interrupt_vector(12'hfff) // 指定中断入口地址 
) psm_soc_u1 (
    .clk (clk) ,
    .reset(~rst_n ) ,
    .in_port (in_port ),
    .out_port(out_port) ,
    .port_id (port_id ),
    .write_strobe(write_strobe) ,
    .interrupt(interrupt) ,
    .interrupt_ack()
); 


bus_mux_3 u_bus_mux_3  (
    .clk( clk ) , 
    .rst_n( rst_n) ,
    .m_dat_i( out_port)  ,  
    .m_dat_o( in_port) ,   
    .m_adr_i( port_id) , 
    .m_wen_i( write_strobe)    ,
                 
    //bus slave 0 output          
    .s0_dat_o( s0_dat)  , 
    .s0_dat_i( s0_rdt)  , 
    .s0_adr_o( s0_adr) , 
    .s0_wen_o( s0_wen)  ,
                 
    //bus slave 0 address configuration
    .s0_addr    ( s0_addr), // Slave address prefix
    .s0_addr_msk( s0_addr_msk), // Slave address prefix mask
                 
    //bus slave 1 output          
    .s1_dat_o( s1_dat)  , 
    .s1_dat_i( s1_rdt)  , 
    .s1_adr_o( s1_adr) , 
    .s1_wen_o( s1_wen)  ,
                 
    //bus slave 1 address configuration
    .s1_addr    ( s1_addr), // Slave address prefix
    .s1_addr_msk( s1_addr_msk), // Slave address prefix mask
                 
    //bus slave 2 output          
    .s2_dat_o( s2_dat)  , 
    .s2_dat_i( s2_rdt)  , 
    .s2_adr_o( s2_adr) , 
    .s2_wen_o( s2_wen)  ,
                 
    //bus slave 2 address configuration
    .s2_addr    ( s2_addr), // Slave address prefix
    .s2_addr_msk( s2_addr_msk)  // Slave address prefix mask
)  ;

bus_gpio  u_bus_gpio1(
    .clk ( clk ), 
    .rst_n(rst_n) , 

    .m_dat_i( s0_dat)  , 
    .m_dat_o( s0_rdt)  , 
    .m_adr_i( s0_adr) , 
    .m_wen_i( s0_wen)  ,

    .gpio0(gpio0)
) ;

bus_led  u_bus_led(
    .clk ( clk ), 
    .rst_n(rst_n) , 

    .m_dat_i( s1_dat)  , 
    .m_dat_o( s1_rdt)  , 
    .m_adr_i( s1_adr) , 
    .m_wen_i( s1_wen)  ,

    .led(gpio1)
) ;


bus_isr u_bus_isr(
    .clk ( clk ), 
    .rst_n(rst_n) , 

    .m_dat_i( s2_dat)  , 
    .m_dat_o( s2_rdt)  , 
    .m_adr_i( s2_adr)  , 
    .m_wen_i( s2_wen)  ,

    // 
    .isr_req_i( isr) ,
    .interrupt_o (interrupt)
) ;


endmodule
 
